december 2010 ? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 nc7sz00 ? tinylogic ? uhs two-input nand gate nc7sz00 tinylogic ? uhs two-input nand gate features ? ultra-high speed: t pd 2.4ns (typical) into 50pf at 5v v cc ? high output drive: 24ma at 3v v cc ? broad v cc operating range: 1.65v to 5.5v ? matches performance of lcx operated at 3.3v v cc ? power down high-impedance inputs/outputs ? over-voltage tolerance inputs facilitate 5v to 3v translation ? proprietary noise/emi reduction circuitry ? ultra-small micropak? packages ? space-saving sot23 and sc70 packages description the nc7sz00 is a single two-input nand gate from fairchild?s ultra-high speed (uhs) series of tinylogic ? . the device is fabricated with advanced cmos technology to achieve ultra-high speed with high output drive while maintaining low static power dissipation over a broad v cc operating range. the device is specified to operate over the 1.65v to 5.5v v cc operating range. the inputs and output are high impedance when v cc is 0v. inputs tolerate voltages up to 6v, independent of v cc operating voltage. related resources ? ms-503 ? family characteristics tinylogic? hs/hst and uhs series ordering information part number top mark package packing method nc7sz00m5x 7z00 5-lead sot23, jedec mo-178 1.6mm 3000 units on tape & reel nc7sz00p5x z00 5-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel nc7sz00l6x yy 6-lead micropak?, 1.00mm wide 5000 units on tape & reel nc7sz00fhx yy 6-lead, micropak2?, 1x1mm b ody, .35mm pitch 5000 units on tape & reel
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 2 nc7sz00 ? tinylogic ? uhs two-input nand gate connection diagrams ieee/iec figure 1. logic symbol pin configurations figure 2. sc70 and sot23 (top view) figure 3. micropak? (top through view) pin definitions pin # sc70 / sot23 pin # micropak? name description 1 1 a input 2 2 b input 3 3 gnd ground 4 4 y output 5 6 v cc supply voltage 5 nc no connect function table inputs output a b y l l h l h h h l h h h l h = high logic level l = low logic level
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 3 nc7sz00 ? tinylogic ? uhs two-input nand gate absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 6.0 v v in dc input voltage -0.5 6.0 v v out dc output voltage -0.5 6.0 v i ik dc input diode current v in < -0.5v -50 ma v in > 6.0v +20 i ok dc output diode current v out < -0.5v -50 ma v out > 6v, v cc =gnd +20 i out dc output current 50 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature (sol dering, 10 seconds) +260 c p d power dissipation at +85c sot-23 200 mw sc70-5 150 micropak?-6 130 micropak2?-6 120 esd human body model, jedec:jesd22-a114 4000 v charge device model, jedec:jesd22-c101 2000 recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage operating 1.65 5.50 v supply voltage data retention 1.5 5.5 v in input voltage 0 5.5 v v out output voltage 0 v cc v t a operating temperature -40 +85 c t r , t f input rise and fall times v cc at 1.8v, 2.5v 0.2v 0 20 ns/v v cc at 3.3v 0.3v 0 10 v cc at 5.0v 0.5v 0 5 ja thermal resistance sot-23 300 c/w sc70-5 435 micropak?-6 500 micropak2?-6 560 note: 1. unused inputs must be held high or low. they may not float.
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 4 nc7sz00 ? tinylogic ? uhs two-input nand gate dc electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to +85c units min. typ. max. min. max. v ih high level input voltage 1.65 to 1.95 0.75v cc 0.75v cc v 2.30 to 5.50 0.70v cc 0.70v cc v il low level input voltage 1.65 to 1.95 0.25v cc 0.25v cc v 2.30 to 5.50 0.30v cc 0.30v cc v oh high level output voltage 1.65 v in =v il i oh =-100a 1.55 1.65 1.55 v 1.80 1.70 1.80 1.70 2.30 2.20 2.30 2.20 3.00 2.90 3.00 2.90 4.50 4.40 4.50 4.40 1.65 i oh =-4ma 1.29 1.52 1.29 1.80 i oh =-8ma 1.90 2.15 1.90 2.30 i oh =-16ma 2.40 2.80 2.40 3.00 i oh =-24ma 2.30 2.68 2.30 4.50 i oh =-32ma 3.80 4.20 3.80 v ol low level output voltage 1.65 v in =v ih i ol =100a 0.00 0.10 0.08 v 2.30 0.00 0.10 0.10 3.00 0.00 0.10 0.10 3.00 0.00 0.10 0.10 4.50 0.00 0.10 0.10 1.65 i ol =4ma 0.80 0.24 0.24 2.30 i ol =8ma 0.10 0.30 0.30 3.00 i ol =16ma 0.15 0.40 0.40 3.00 i ol =24ma 0.22 0.55 0.55 4.50 i ol =32ma 0.22 0.55 0.55 i in input leakage current 0 to 5.5 v in =5.5v, gnd 1 10 a i off power off 0 v in or v out =5.5v 1 10 a i cc quiescent supply current 1.65 to 5.50 v in =5.5v, gnd 2 20 a
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 5 nc7sz00 ? tinylogic ? uhs two-input nand gate ac electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to +85c units figure min. typ. max. min. max. t phl , t plh propagation delay 1.65 c l =15pf, r l =1m 2.0 5.4 11.4 2.0 12.0 ns figure 4 figure 5 1.80 2.0 4.5 9.5 2.0 10.0 2.50 0.20 0.8 3.0 6.5 0.8 7.0 3.30 0.30 0.5 2.4 4.5 0.5 4.7 5.00 0.50 0.5 2.0 3.9 0.5 4.1 3.30 0.30 c l =50pf, r l =500 1.5 2.9 5.0 1.5 5.2 5.00 0.50 0.8 2.4 4.3 0.8 4.5 c in input capacitance 0.00 4 pf c pd power dissipation capacitance (2) 3.30 24 pf figure 6 5.00 30 note: 2. c pd is defined as the value of the internal equivalent capacitance derived from dynamic operating current consumption (i ccd ) at no output lading and operating at 50% duty cycle. c pd is related to i ccd dynamic operating current by the expression: i ccd =(c pd )(v cc )(f in )+(i cc static). figure 4. ac test circuit figure 5. ac waveforms note: 3. input=ac waveform; t r =t f =1.8ns; prr=10mhz; duty cycle =50%. figure 6. i ccd test circuit
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 6 nc7sz00 ? tinylogic ? uhs two-input nand gate physical dimensions 5 1 4 3 2 land pattern recommendation b a l c 0.10 c 0.20 cab 0.60 ref 0.55 0.35 seating plane 0.25 gage plane 8 0 notes: unless othewise specified a) this package conforms to jedec mo-178, issue b, variation aa, b) all dimensions are in millimeters. 1.45 max 1.30 0.90 0.15 0.05 1.90 0.95 0.50 0.30 3.00 2.60 1.70 1.50 3.00 2.80 symm c 0.95 0.95 2.60 0.70 1.00 see detail a 0.22 0.08 c) ma05brev5 top view (0.30) figure 7. 5-lead sot23, jedec mo-178 1.6mm package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/sot23-5l_tr.pdf . package designator tape section cavity number cavity status cover type status m5x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 7 nc7sz00 ? tinylogic ? uhs two-input nand gate physical dimensions figure 8. 5-lead, sc70, eiaj sc-88a, 1.25mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf . package designator tape section cavity number cavity status cover type status p5x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 8 nc7sz00 ? tinylogic ? uhs two-input nand gate physical dimensions 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 9. 6-lead, micropak?, 1.0mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 9 nc7sz00 ? tinylogic ? uhs two-input nand gate physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 6 54 0.35 (0.08) 4x side view figure 10. 6-lead, micropak2, 1x1mm body, .35mm pitch package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 1996 fairchild semiconductor corporation www.fairchildsemi.com nc7sz00 ? rev. 1.0.4 10 nc7sz00 ? tinylogic ? uhs two-input nand gate
|
